千核级处理器的高效模拟关键技术研究

项目名称： 千核级处理器的高效模拟关键技术研究

项目编号： No.61202125

项目类型： 青年科学基金项目

立项/批准年度： 2013

项目学科： 计算机科学学科

项目作者： 赵天磊

作者单位： 中国人民解放军国防科学技术大学

项目金额： 23万元

中文摘要： 近年来，片上多核及众核体系结构成为国内外的研究热点。而根据摩尔定律，单芯片上集成的处理器核数目将呈指数级增加，千核级处理器已不再遥远。随着处理器核数目的增加，传统串行模拟器在模拟此类结构时的性能会急剧恶化。与此同时，千核级处理器的体系结构设计空间却扩大了数倍。因此，体系结构设计空间探索的效率将会非常低，模拟器这一重要研究手段将面临巨大挑战。 本课题提出一个面向千核级体系结构的分布式并行模拟加速框架，利用 Host 平台的并行计算能力来开发目标机模型中天然存在的粗粒度并行性，以提高模拟器的速度。重点突破目标机模型动态自适应划分技术、Host并行层次与拓扑结构感知的模型映射技术、保守与乐观相结合的高效模拟时间同步技术，以及模拟负载动态平衡技术。研究成果将对国产多核众核微处理器设计起到重要的基础支撑作用。

中文关键词： 模拟器；功能模拟；性能模拟；并行模拟；协同验证

英文摘要： Chip multicore and manycore has been the hotspot of computer architecture research in recent years. According to Mooler's law, the number of cores that can be integrated on a single chip will increase in expoential order. The thousands-core per chip era is not far away any more. As the number of cores increases, the speed of traditional sequential simulators will degrade drastically. On the other hand, the design space of thousands-core processors is several times larger. Consequently, the efficiency of design space exploration will be very low. Computer architecture simulators, as an important computer architecture research tool, are facing serious challenges. This project proposes a framework for parallel and distributed simulation of thousands-core chips. The basic idea is to exploit the parallelism that lies naturally in the target architecture model with the parallel computing capability of the host system. The main challenges are dynamic and adaptive target model partition technique, parallel hierachy and topology aware model mapping, pessimistic and optimistic coordinated highly efficient simulation time synchronization technique, and dynamic simulation load balance technique. The research result of this project will build an important infrastructure for domestic multicore and manycore processor design.

英文关键词： simulator；functional simulation；performance simulation；parallel simulation；co-verification