CodeAPeel:计算机建筑课程综合和多层学习技术 (CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses)

In this paper, we introduce a versatile, multi-layered technology to help support teaching and learning computer architecture concepts. This technology, called CodeAPeel is already implemented in one particular form to describe instruction processing in assembly and machine layers by a comprehensive simulation of fetch-decode-execute process as well as animation of the behavior of CPU registers, RAM, VRAM, STACK memories, and various control registers of a generic instruction set architecture. Unlike most educational CPU simulators, CodeAPeel does not simulate a real processor such as MIPS or RISC-V, but it is designed and implemented as a generic RISC instruction set architecture with both scalar and vector operands, making it a dual architecture, supporting Flynn's SISD and SIMD instruction set architectures.

翻译：在本文中,我们引入了一个多功能、多层次的技术来帮助支持教学和学习计算机结构概念。这个称为CodeAPeel的技术已经以一种特殊的形式得到应用,以描述组装和机器层的教学处理,其方法是全面模拟抓取-decode-Execute 过程以及CPU 登记册、 RAM、 VRAM、 STACK 记忆和通用指令集结构的各种控制登记册的动画。与大多数教育性的CPU模拟器不同, CodeAPeel 不模拟真正的处理器, 如MIPS 或RISC-V, 但它被设计并作为一种通用的RISC 指令集结构来描述组装和机器层的教学处理, 包括标语和矢量操作, 使它成为一个双重结构, 支持Flynn的SISD和SIMD 指令集结构。