The P4 language has drastically changed the networking field as it allows to quickly describe and implement new networking applications. Although a large variety of applications can be described with the P4 language, current programmable switch architectures impose significant constraints on P4 programs. To address this shortcoming, FPGAs have been explored as potential targets for P4 applications. P4 applications are described using three abstractions: a packet parser, match-action tables, and a packet deparser, which reassembles the output packet with the result of the match-action tables. While implementations of packet parsers and match-action tables on FPGAs have been widely covered in the literature, no general design principles have been presented for the packet deparser. Indeed, implementing a high-speed and efficient deparser on FPGAs remains an open issue because it requires a large amount of interconnections and the architecture must be tailored to a P4 program. As a result, in several works where a P4 application is implemented on FPGAs, the deparser consumes a significant proportion of chip resources. Hence, in this paper, we address this issue by presenting design principles for efficient and high-speed deparsers on FPGAs. As an artifact, we introduce a tool that generates an efficient vendor-agnostic deparser architecture from a P4 program. Our design has been validated and simulated with a cocotb-based framework. The resulting architecture is implemented on Xilinx Ultrascale+ FPGAs and supports a throughput of more than 200 Gbps while reducing resource usage by almost 10$\times$ compared to other solutions.
翻译:P4 语言在快速描述和实施新的网络应用程序时大大改变了网络字段。虽然可以用P4语言描述大量各种应用程序,但目前的可编程开关结构对P4程序施加了重大限制。为解决这一缺陷,已经探索了P4应用程序的潜在目标。P4 应用程序使用三个抽象来描述:一个包包包包、配对操作表和一个包拆解器,它们根据匹配操作表的结果重新组合了美元产出包。尽管对FPGAs的包拆解析器和配对操作表的实施在文献中已广泛覆盖,但对PFPGAs软件的配置却没有提出任何一般性的设计原则。事实上,在FPG应用程序上实施高速高效的拆分解器仍然是个未解决的问题,因为它需要大量的互连和结构必须适应一个P4程序。结果是,在一些工作中,在FP4 基GGGAs 上实施一个P4 应用程序,而DP4 将相当一部分的芯片资源在文献中被广泛使用,因此,我们通过一个高效的SAFA 格式,我们通过一个高效的模型来展示这个工具的版本。