We present Calyx, a new intermediate language (IL) for compiling high-level programs into hardware designs. Calyx combines a hardware-like structural language with a software-like control flow representation with loops and conditionals. This split representation enables a new class of hardware-focused optimizations that require both structural and control flow information which are crucial for high-level programming models for hardware design. The Calyx compiler lowers control flow constructs using finite-state machines and generates synthesizable hardware descriptions. We have implemented Calyx in an optimizing compiler that translates high-level programs to hardware. We demonstrate Calyx using two DSL-to-RTL compilers, a systolic array generator and one for a recent imperative accelerator language, and compare them to equivalent designs generated using high-level synthesis (HLS). The systolic arrays are $4.6\times$ faster and $1.1\times$ larger on average than HLS implementations, and the HLS-like imperative language compiler is within a few factors of a highly optimized commercial HLS toolchain. We also describe three optimizations implemented in the Calyx compiler.
翻译:Calyx是用于将高级程序编集成硬件设计的一种新型中间语言。 Calyx 将硬件类结构语言与软件类控制流程代表器、环形和有条件的流程代表器相结合。这种分割代表器可以提供新型的硬件焦点优化,既需要结构信息,也需要对硬件设计高级编程模型至关重要的控制流程信息。 Calyx 编译器使用有限状态机器降低控制流程结构,并生成可合成硬件描述。我们在一个将高级程序翻译为硬件的优化编译器中实施了Calex 。我们用两个 DSL-RTL 编译器演示了Calex, 一个套式阵列生成器,一个是最近需要的加速语言,并将它们与使用高级合成(HLS)生成的等量设计进行比较。 Systelic 阵列的平均执行速度为4.6美元,比HLS要快110美元,而像 HLS 一样的紧急语言编译器是在高度优化的商用 HLS 工具链的几个因素中安装的。我们还描述了在CAx 中执行的三种最优化。